RAKE receiver device

ABSTRACT

A RAKE receiver device includes a plurality of fingers for demodulating multipath receive data, and a data synthesis circuit for synthesizing the receive data from each of the paths and demodulated by the plural fingers. Each time the receive data is demodulated by one of the plural fingers, the data synthesis circuit adds cumulatively the demodulated receive data for each identical receive data from each of the paths, and synthesizes the data.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a RAKE receiver device used in a mobilecommunications system employing spectrum spreading technology.

2. Description of the Related Art

In communications method employing spectrum spreading technology,modulated and spread data (i.e., a signal) is sent from a sending end,and the data received on a receiving end is de-spread and demodulated,whereby sending and receiving of data is performed. In thecommunications method employing such spectrum spreading technology, thefrequency spectrum of the data is spread into a wide range so thatexcellent anti-interference property and communications privacy areensured, thus having an advantage that multiple users can share achannel in the same frequency band. Therefore, in recent years, thiscommunications method has been widely utilized in a mobilecommunications system such as a portable telephone or the other thing.

An example of the communications method utilizing this spectrumspreading technology includes CDMA (Code Division Multiple Access).

Incidentally, in mobile communications, wireless communication usingradio waves is performed between a base station and a terminal such as aportable telephone or the other thing. In this case, the radio waves mayarrive at the receiving end by propagating linearly or by beingreflected by a construction such as a building or the other thing forexample. Therefore, the receiving end receives multiple signals whichhave been transmitted through a plurality of paths (multiple paths).Since these radio waves have time lags (phase differences) caused by thedifferences in the distances they have traveled, a phenomenon calledfading occurs such that they strengthen each other when they are inphase with each other, and when they are out of phase from each otherthey weaken each other.

By contrast, in the mobile communications system that utilizes thespectrum spreading technology, there is used a method called a RAKEreceiver system, in which a plurality of receive data transmittedthrough multiple paths are synthesized to thereby improve quality ofcommunication. A RAKE receiver device which employs the RAKE receiversystem has a plurality of fingers corresponding to the number ofassociated paths, and each of the fingers demodulates receive data fromeach associated path. The phase differences of the received anddemodulated data are corrected, and the data which phase differenceshave been corrected are synthesized.

For example, a receiver device, a receiver method and a terminal deviceof a portable telephone system disclosed in JP 10-209919 A, and a CDMAsystem communications apparatus disclosed in JP 11-331124 A are known asconventional techniques employing the RAKE receiver system.

Each of the RAKE receiver devices disclosed in these publications hasone memory provided for each finger, for storing the receive data. Thereceive data from each path and demodulated by the finger for each pathis held in each memory associated with that finger. After the receivedata from the chronologically last path has been stored in the memory,identical receive data are read out from all memories, and the identicalreceive data from all the paths are added together and synthesized.

Thus, in the conventional RAKE receiver device, a massive amount ofmemory is used for each finger. Therefore, there was a problem that thescale of the circuitry increased, and, as a result, power consumptionwas enormous as well.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a RAKE receiverdevice which resolves the problems with the above-mentioned conventionaltechnique, so as to reduce the scale of the circuitry and thereforepower consumption.

In order to achieve the above-mentioned object, according to the presentinvention, there is provided a RAKE receiver device comprising: aplurality of fingers for demodulating receive data from multiple paths;and a data synthesis circuit for synthesizing the receive data from eachof the paths and demodulated by the plurality of fingers, wherein eachtime that the receive data of each path is demodulated by one of theplurality of fingers, the data synthesis circuit adds cumulatively thedemodulated receive data for each identical receive data from each ofthe paths, and synthesizes the data.

Further, according to the present invention, there is provided a RAKEreceiver device comprising: a plurality of fingers for demodulatingreceive data of multiple paths; a data synthesis circuit forsynthesizing the receive data from each of the paths and demodulated bythe plurality of fingers; and a timing adjustment circuit for adjustingtiming when the receive data from each of the paths and demodulated bythe plurality of fingers are provided to the data synthesis circuit,wherein that the timing adjustment circuit holds the receive data fromeach of the paths and demodulated by the fingers; and each time that thereceive data from each of the paths and demodulated by the plurality offingers are supplied from the timing adjustment circuit, the datasynthesis circuit adds cumulatively the demodulated receive data foreach identical receive data from each of the paths, and synthesizes thedata.

Here, it is preferable that the data synthesis circuit comprises onememory that is shared by the fingers, and each time the receive datafrom each of the paths are demodulated by the plurality of fingers,cumulatively added data is read out from each corresponding memoryaddress, added to the demodulated identical receive data from each ofthe paths, and written back into the same respectively correspondingaddress of the memory.

Further, it is desirable that the fingers are set in advance withpriority order, and the data synthesis circuit adds cumulatively, one ata time and in chronological order, the identical receive data from eachof the paths and demodulated by the plurality of fingers, and when twoor more demodulated receive data from each of the paths are inputtedsimultaneously, the data synthesis circuit sequentially addscumulatively the demodulated receive data from each of the paths foreach identical receive data, according to the priority order.

Further, according to the present invention, there is provided a RAKEreceiver device comprising: a plurality of fingers for demodulatingreceive data from multiple paths; a data synthesis circuit forsynthesizing the receive data from each of the paths and demodulated bythe plurality of fingers; and a timing adjustment circuit for adjustingtiming when the receive data from each of the paths and demodulated bythe plurality of fingers are provided to the data synthesis circuit,wherein the plurality of fingers demodulate a plurality of receive dataper 1 symbol time unit, the timing adjustment circuit holds theplurality of receive data from each of the paths and demodulated by theplurality of fingers, and each time that the receive data from each ofthe paths and demodulated by the plurality of fingers are supplied fromthe timing adjustment circuit, the data synthesis circuit addscumulatively the demodulated receive data for each identical receivedata from each of the paths, and synthesizes the data.

Here, it is desirable that the data synthesis circuit comprises onememory shared by the plurality of fingers, wherein each time that thereceive data from each of the paths and demodulated by the plurality offingers are supplied from the timing adjustment circuit, cumulativelyadded data is read out from each corresponding memory address, added tothe demodulated identical receive data from each of the paths, andwritten back into the same respectively corresponding address of thememory.

Further, it is preferable that the plurality of fingers and theplurality of receive data are each set in advance with priority order,the data synthesis circuit receives from the timing adjustment circuitthe demodulated receive data from each of the paths and addscumulatively them one at a time and in chronological order, when two ormore of the demodulated receive data from each of the paths are held inthe timing adjustment circuit, the data synthesis circuit sequentiallyreceives, from the timing adjustment circuit, the same-priority-orderdemodulated receive data of the plurality of fingers according to thepriority order of the fingers, further repeats this operation accordingto the priority order of the receive data, and sequentially addscumulatively the demodulated receive data from each of the paths foreach identical receive data.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is a constructional outline diagram of an embodiment of the RAKEreceiver device according to the present invention;

FIG. 2 is a conceptual diagram showing timing of receive datademodulated by each finger, according to an embodiment of the invention;

FIG. 3 is a constructional outline diagram of another embodiment of theRAKE receiver device of the present invention;

FIG. 4 is a timing chart showing operation of a FIFO device, accordingto an embodiment of the invention;

FIG. 5 is a timing chart showing operation of the RAKE receiver deviceshown in FIG. 3, according to an embodiment of the invention; and

FIG. 6 is a timing chart showing operation of the RAKE receiver deviceshown in FIG. 3, according to another embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a RAKE receiver device according to the present inventionwill be described in detail, based on preferred embodiments thereofillustrated in the attached drawings.

FIG. 1 is a constructional outline diagram of an embodiment of a RAKEreceiver device of the present invention.

A RAKE receiver device 10 shown in the diagram has three fingers (FINGER0, FINGER 1, FINGER 2) 12 a, 12 b, and 12 c and a data synthesis circuit14. According to the RAKE receiving method, each time receive data isdemodulated by one of the plural fingers, the RAKE receiver devicecumulates and synthesizes the demodulated data for identical receivedata of each path.

In the RAKE receiver device 10 shown in the diagram, each of the fingers12 a, 12 b, and 12 c demodulate multipath receive data. The demodulatedreceive data are inputted into the data synthesis circuit 14. Note that,for the fingers, any of the conventional, publicly known constructionsmay be used. Further, in the example shown in the diagram, three fingers12 a, 12 b, and 12 c corresponding to three paths are provided, but thenumber of the fingers may be modified appropriately as needed.

On the other hand, the data synthesis circuit 14 has a selector 16, anadder 18, a selector 20, a memory (a dualport RAM) 22, and two addresscontrollers (ADDR CTL 0,1) 24 a and 24 b. Each time the receive data isdemodulated by one of the fingers 12 a, 12 b, and 12 c, the datasynthesis circuit 14 cumulates and synthesizes the demodulated receivedata for each identical receive data in each path.

Here, the demodulated receive data of each path, which are inputted fromthe fingers 12 a, 12 b, and 12 c, are outputted one by one inchronological sequence from the selector 16. Further, in a case wherethe demodulated receive data are inputted simultaneously from aplurality of the fingers, the demodulated receive data is outputted insequence selectively starting with the demodulated receive data from thehighest priority finger, according to the predetermined order ofpriority with respect to the fingers 12 a, 12 b, and 12 c. There is norestriction regarding the order of priority, but, in this embodiment, itis finger 12 a, 12 b, and then finger 12 c, in order of decreasingpriority.

Then, the receive data of each path and demodulated by one of thefingers 12 a, 12 b, and 12 c are inputted to the adder 18 in sequencevia the selector 16. The adder 18 adds the demodulated data anddemodulated identical receive data from another path or data obtained bycumulatively adding together identical receive data from a plurality ofother paths, which has been read out from the memory 22 by control fromthe address controller 24 a, as will be described in detail below. Anoutput signal from the adder 18 is inputted into a terminal 0 of thesubsequent selector 20.

The selector 20 selectively outputs either the output signal from theadder 18 that was inputted into the terminal 0 thereof, or an outputsignal of the selector 16 that was inputted into a terminal 1 thereof.At the time when the first receive data has been demodulated by one ofthe fingers 12 a, 12 b, and 12 c, the memory 22 is not holdingdemodulated receive data from other paths that are identical data withthe first demodulated receive data. In this case, the output signal fromthe selector 16 is outputted via the selector 20. In any other case, theoutput signal from the adder 18 is outputted via the selector 20.

The memory 22 holds the output signal from the selector 20 by a controlof the address controllers 24 a and 24 b. Therefore, in the case of theexample shown in the diagram, a dualport RAM is used as the memory 22.The data read out from the memory 22 by the control of the addresscontroller 24 a is inputted into the adder 18 as described above. Thedata that was read out from the memory 22 by the control of the addresscontroller 24 b is outputted as a synthesized data.

The address controllers 24 a and 24 b control an operation of the memory22 as described above. Here, the address controller 24 a controls thewriting (W) of the output signal from the selector 20 to the memory 22,and the reading (R) of the data from the memory 22 which is inputtedinto the adder 18. The address controller 24 b controls the reading (R)of the data from the memory 22 which is to become the synthesizedreceive data from the RAKE receiver device 10.

Note that, in accordance with this embodiment, the dual port RAM is usedas the memory 22, and the two address controllers 24 a and 24 b are usedto control the operation of the dual port RAM. However, the invention isnot limited to this configuration. For example, if a function is addedfor arbitrating between the address controller 24 a and the addresscontroller 24 b, then a single port RAM may also be used as the memory22. Further, it is also possible to control the operation of the memory22 with one address controller.

Next, an operation of the RAKE receiver device 10 according to thepresent invention will be described, referring to a conceptual diagramshown in FIG. 2.

In an example shown in FIG. 2, receive data is demodulated by the finger12 a (FINGER 0), in the order of receive data D0, and then receive dataD1. Further, the receive data D0 is demodulated by the finger 12 b(FINGER 1) at a timing when the finger 12 a demodulates the receive dataD1, and then D1 is demodulated by the finger 12 b. Similarly, thereceive data D0 is demodulated by the finger 12 c (FINGER 2) at a timingwhen the finger 12 b demodulates the receive data D1, and then D1 isdemodulated by the finger 12 c.

First, the receive data D0 is demodulated by the finger 12 a. Thisreceive data D0 is the first receive data D0 of three receive data D0which are to be demodulated by all the fingers 12 a, 12 b, and 12 c.Therefore, the memory 22 does not have the demodulated receive data D0from the other paths except this path. Therefore, this demodulatedreceive data D0 is inputted to the memory 22 via the selectors 16, 20,and is written into its address 0 by the control of the addresscontroller 24 a.

At this point, the address 0 of the memory 22 holds the receive data D0demodulated by the finger 12 a.

Then, at a timing when the receive data D1 is demodulated by the finger12 a, the receive data D0 is demodulated by the finger 12 b. Asdescribed already, in accordance with this embodiment, the priorityorder is set as finger 12 a, 12 b, and then 12 c, in that order.Therefore, the receive data D1 demodulated by the finger 12 a is firstoutputted from the selector 16, and then the receive data D0 demodulatedby the finger 12 b is outputted next.

Note that, processing time needed for the data synthesis circuit 14 tosynthesize the demodulated receive data is extremely shorter thanprocessing time needed for the fingers 12 a, 12 b, and 12 c todemodulate the receive data. Therefore, even in a case where two receivedata are demodulated simultaneously, no problem will occur, even if thesimultaneously demodulated receive data are processed in order accordingto the order of priority. This is the same in the case where three ormore receive data are demodulated simultaneously.

As described above, first, the receive data D1 that was demodulated bythe finger 12 a is processed by the data synthesis circuit 14. Thedemodulated receive data D1 is the first demodulated receive data D1from among the three receive data D1 to be demodulated by all thefingers 12 a, 12 b, and 12 c, like the demodulated receive data D0.Therefore, it is inputted into the memory 22 via the selector 20, andwritten into the address 1 of the memory 22 by the control of theaddress controller 24 a.

At this point, the address 1 of the memory 22 holds the receive data D1demodulated by the finger 12 a.

Next, the receive data D0 demodulated by the finger 12 b is processed.Since this demodulated receive data D0 is not the first demodulatedreceive data D0, it is inputted into the adder 18. At this time, thedemodulated receive data D0 being held in the address 0 of the memory 22is read out and inputted into the adder 18 by the control of the addresscontroller 24 a. Then, the both receive data D0 are added together bythe adder 18, inputted into the memory 22 via the selector 20, andwritten again into the same address 0.

At this point, the address 0 of the memory 22 holds data produced byadding the receive data D0 demodulated by the finger 12 a and thereceive data D0 demodulated by the finger 12 b.

Note that, since the demodulated receive data D0 and the demodulatedreceive data D1 are different data, they are held respectively indifferent addresses 0 and 1 of the memory 22. Further, the receive dataD0 of each path demodulated by the fingers 12 a, 12 b, and 12 c are thesame data. Therefore, they are added cumulatively and written into thesame address 0 of the memory 22. Similarly, since the receive data D1 ofeach path demodulated by the fingers 12 a, 12 b, and 12 c are the samedata, they are added cumulatively and written into the identical address1 of the memory 22.

Then, at a timing when the receive data D1 is demodulated by the finger12 b, the receive data D0 is demodulated by the finger 12 c. From theselector 16, the receive data D1 demodulated by the finger 12 b isoutputted first, and then the receive data D0 demodulated by the finger12 c is outputted in sequence.

First, the receive data D1 demodulated by the finger 12 b is processed.Since this demodulated receive data D1 is not the first demodulatedreceive data D1, it is inputted into the adder 18. At the same time, thedemodulated receive data D1 being held in the address 1 of the memory 22is read out and inputted into the adder 18 by the control of the addresscontroller 24 a. Then, the both demodulated receive data D1 are addedtogether by the adder 18, inputted into the memory 22 via the selector20, and written again into the same address 1.

At this point, the address 1 of the memory 22 holds data produced byadding together the receive data D1 demodulated by the finger 12 a andthe receive data D1 demodulated by the finger 12 b.

Next, the receive data D0 demodulated by the finger 12 c is processed.Since this demodulated receive data D0 is also not the first demodulatedreceive data D0, it is inputted into the adder 18. At the same time, thedemodulated receive data D0 being held in the address 0 of the memory 22is read out and inputted into the adder 18 by the control of the addresscontroller 24 a. Then, the both demodulated receive data D0 are addedtogether by the adder 18, inputted into the memory 22 via the selector20, and written again into the same address 0.

At this point, the address 0 of the memory 22 holds data produced byadding cumulatively all the receive data D0 demodulated by each of thefingers 12 a, 12 b, and 12 c.

After the data obtained by adding cumulatively all the demodulatedreceive data D0 is written into the address 0 of the memory 22, thedemodulated receive data D0 being held in the address 0 of the memory 22is read out and outputted as synthesized demodulated receive data D0 bythe control of the address controller 24 b.

Finally, the receive data D1 is demodulated by the finger 12 c. Sincethis demodulated receive data D1 is also not the first demodulatedreceive data D1, it is inputted into the adder 18. At the same time, thedemodulated receive data D1 being held in the address 1 of the memory 22is read out and inputted into the adder 18 by the control of the addresscontroller 24 a. Then, the both demodulated receive data D1 are addedtogether by the adder 18, inputted into the memory 22 via the selector20, and written again into the same address 1.

At this point, the address 1 of the memory 22 holds data produced byadding cumulatively all the receive data D1 demodulated by each of thefingers 12 a, 12 b, and 12 c.

After the data produced by adding cumulatively all the demodulatedreceive data D1 is written into the address 1 of the memory 22, thedemodulated receive data D1 being held in the address 1 of the memory 22is similarly read out and outputted as the synthesized demodulatedreceive data D1 by the control of the address controller 24 b.

Next, referring to another example of the RAKE receiver device accordingto the present invention, for example, time division processing in whichmultiple receive data are demodulated by plural fingers per one symboltime unit will be described.

For example, in a case where data that has been modulated by a QPSK(Quadrature Phase Shift Keying) method is sent from a sending sourcesuch as a base station or other, two signals I and Q are simultaneouslydemodulated per one symbol time unit by the fingers at a reception pointsuch as a mobile phone or other.

Therefore, in the communications employing the QPSK method, two receivedata are simultaneously demodulated by respective fingers, and these twodemodulated receive data are outputted as a unit in sequence from thefingers.

Further, in standard specifications for 3rd generation mobilecommunications systems (3GPP), there is employed a diversity methodcommunications technique in which the base station uses two antennas atmaximum to send a downlink signal. In STTD (space time transmitdiversity) that is one open-loop mode of the diversity method, forexample, one data per symbol time unit is sent from each of the basestation's two antennas, that is, a total of two data per symbol timeunit are sent to the mobile phone.

Further, one of the two data sent from these two antennas is sent justas it is, for example, and the other one is sent after chronologicallyswitching the sequence of data of two symbol time units, inverting thepositivity and negativity, and performing complex conjugate processing.Therefore, at the mobile phone, when the two data for the one symboltime unit from the two antennas are received, demodulation of the datacannot be executed at that point, but the data can be demodulated at thetime when the total of four data for two symbol time unit units arereceived.

Therefore, in the case where STTD is used in the 3GPP, the four receivedata are simultaneously demodulated by each of the fingers, and thedemodulated four receive data are outputted as a unit in sequence fromthe fingers.

The following description is directed to an example in which fourreceive data are simultaneously demodulated per two symbol time units(i.e., two receive data per one symbol time unit) by four fingers, as inthe abovementioned case where the STTD is used in the 3GPP.

FIG. 3 is a constructional outline diagram of another embodiment of theRAKE receiver device according to the present invention.

A RAKE receiver device 30 shown in FIG. 3 represents an adaptation ofthe RAKE receiver device 10 shown in FIG. 1 such that it is furtherconfigured to adjust timing when receive data demodulated by the fingersare outputted to the data synthesis circuit. The RAKE receiver device 30has four fingers (FINGER 0, FINGER 1, FINGER 2, and FINGER 3) 32 a, 32b, 32 c, and 32 d, a timing adjustment circuit 34, and a data synthesiscircuit 36.

In the RAKE receiver device 30 shown in FIG. 3, the fingers 32 a, 32 b,32 c, and 32 d differ from the fingers 12 a, 12 b, and 12 c shown inFIG. 1 only in that their number has been modified from 3 to 4. Notethat, the number of the fingers is subject to no restriction as far asit is two or larger. The demodulated receive data which are outputtedfrom the fingers 32 a, 32 b, 32 c, and 32 d are inputted into the timingadjustment circuit 34.

The timing adjustment circuit 34 adjusts the timing when the demodulatedreceive data of each path inputted from the fingers 32 a, 32 b, 32 c,and 32 d are outputted to the data synthesis circuit 36. The timingadjustment circuit 34 includes four FIFO (First-In First-Out) devices 38a, 38 b, 38 c, and 38 d corresponding to each of the fingers 32 a, 32 b,32 c, and 32 d. Note that, the timing adjustment circuit 34 is notrestricted to the FIFO devices, and any memory circuit may be used suchas a dual-port RAM or register file or others.

Further, each time the receive data demodulated by the fingers 32 a, 32b, 32 c, and 32 d are provided from the timing adjustment circuit 34,the data synthesis circuit 36 adds cumulatively and synthesizes thedemodulated receive data for each of identical receive data of eachpath. The data synthesis circuit 36 includes a selector (a priorityencoder) 40, an adder 42, a memory 44, and a control circuit 46.

Here, output signals of the selector 40 and the memory 44 are inputtedinto the adder 42, and an output signal from the adder 42 is inputtedinto the memory 44. Further, from the memory 44, the demodulated receivedata which has been synthesized is outputted. A request signal REQ fromthe timing adjustment circuit 34 is inputted into the control circuit46. From the control circuit 46, control signals CTL1 and CTL2 areoutputted to the selector 40 and to the memory 44, and an acknowledgesignal ACK is outputted to the timing adjustment circuit 34.

The data synthesis circuit 36 differs from the data synthesis circuit 14shown in FIG. 1 in the following three points. Namely, the datasynthesis circuit 36 is not provided with a constituent elementcorresponding to the selector 20. Also, the memory 44 has a function forinitializing data in each of its addresses. Further, in addition to thefunction of the address controllers 24 a and 24 b of the data synthesiscircuit 14 shown in FIG. 1, the control circuit 46 has a function forcontrolling processing for receiving the demodulated receive data bymeans of a handshaking with the above-mentioned timing adjustmentcircuit 34.

Before starting to add cumulatively the demodulated receive data foreach identical receive data of each path, in the data synthesis circuit36, the control signal CTL2 is given from the control circuit 46 to thememory 44, so that the data being held in the corresponding address ofthe memory 44 is initialized (for example, set to “0”). When thecumulation addition is performed, first demodulated receive data amongthe identical receive data and initialized data being held in the memory44 are added together, and this is held again in the correspondingaddress of the memory 44.

As described above, in the data synthesis circuit 36, the memory 44 hasa function to initialize the data being held in each address. However,the invention is not limited to this configuration. For example, it isalso possible to achieve this function by configuring the data synthesiscircuit 36 so that it is equivalent in function to the selector 20 ofthe data synthesis circuit 14 shown in FIG. 1. Note that, the operationof the data synthesis circuit 36 is the same as the operation of thedata synthesis circuit 14 shown in FIG. 1, except the control of theprocessing performed with the timing adjustment circuit 34. Therefore,detailed explanation thereof is omitted.

Next, an operation of the RAKE receiver device 30 shown in FIG. 3 willbe described.

First, referring to a timing chart shown in FIG. 4, the operation of theRAKE receiver device 30 will be explained by focusing on one FIFO device38 a in the timing adjustment circuit 34. In the following explanation,it is assumed that demodulated receive data D0 to D3, D4 to D7, and soon are inputted in this sequence from the finger 32 a to the FIFO device38 a, as shown in FIG. 4, in units composed of four data.

The data synthesis circuit 36 is reset by a low-level signal of a signalRESETN, to be initialized. Further, before starting to add cumulativelythe demodulated receive data for each identical receive data of eachpath, the data synthesis circuit 36 supplies the control signal CTL2from the control circuit 46 to the memory 44, as described above. Inresponse to this, data in the corresponding address of the memory 44 isinitialized. Here, it is assumed that the data in each address of thememory 44 is initialized to “0”.

First, when the demodulated receive data D0 (DIN0) is inputted from thefinger 32 a to the FIFO device 38 a, the demodulated receive data D0 isheld in a write address WA0 of the FIFO device 32 a. Then, a strobesignal STB is outputted, and the write address WA0 is increased innumber at a falling timing of the strobe signal STB, thus changing to awrite address WA1. At the same time, a request signal REQ0 changes to ahigh-level signal and the request signal REQ also changes to ahigh-level signal.

Here, request signals REQ0 to REQ3 are signals respectivelycorresponding to the first through the fourth demodulated receive dataamong the four demodulated receive data (e.g., D0 to D3), and theyindicate that new demodulated receive data which should be addedcumulatively by the data synthesis circuit 36 is being held in the FIFOdevice 38 a. Further, the request signal REQ is an OR (i.e.,disjunction) signal of these request signals REQ0 to REQ3, and it isprovided to the control circuit 46 of the data synthesis circuit 36 asshown in FIG. 3.

When the request signal REQ is provided from the FIFO device 38 a, thecontrol signal CTL1 is provided from the control circuit 46 to theselector 40. In response to this, the demodulated receive data D0(DOUT0) that was read out from the read address RA0 of the FIFO device38 a is selected by and outputted from the selector 40. This data D0 isadded by the adder 42 to the initialized data “0” being held in thecorresponding address of the memory 44, and the result of the addition,which is to say the data D0, is held once again in the same address ofthe memory 44.

Upon the completion of the writing of the addition result to the memory44 (i.e., the cumulation addition of the data D0), the acknowledgesignal ACK is given to the FIFO device 38 a from the control circuit 46.In response to this, a read address RA0 of the FIFO device 38 a isincreased in number at a falling timing of the acknowledge signal ACK soas to change to a read address RA1, and at the same time the requestsignal REQ0 returns to a low-level signal.

The operation is similar thereafter. The remaining data D1 to D3 fromthe four data, which are the data D0 to D3 according to the timing chartshown in FIG. 4, are each held in the write addresses WA1 to WA3 of theFIFO device 38 a respectively, and are read out from the read addressesRA1 to RA3 respectively. At the data synthesis circuit 36 they are addedcumulatively for each identical receive data of each path. Further, thesubsequent four data, which are the data D4 to D7 according to theexample shown in FIG. 4, are similarly processed in sequence.

Next, an operation of the RAKE receiver device 30 will be described byfocusing on mutual relationships between the four FIFO devices 38 a, 38b, 38 c, and 38 d in the timing adjustment circuit 34, referring totiming charts shown in FIG. 5 and FIG. 6. In similar fashion, thedemodulated receive data are simultaneously inputted from the fingers 32a, 32 b, 32 c, and 32 d to the respectively corresponding FIFO devices38 a, 38 b, 38 c, and 38 d, in sequence going from D0 to D3, D4 to D7,and so on, each in units composed of four data.

Here, the diagram of the RAKE receiver device 30 shown in FIG. 3 issimplified, but the request signal REQ is inputted to the controlcircuit 46 from each of the FIFO devices 38 a, 38 b, 38 c, and 38 d.Further, the acknowledge signal ACK is also inputted from the controlcircuit 46 into each of the FIFO devices 38 a, 38 b, 38 c, and 38 d, andthe FIFO devices 38 a, 38 b, 38 c, and 38 d each operate according toindependent timing.

In the timing charts shown in FIG. 5 and FIG. 6, the request signalssupplied from the FIFO devices 38 a, 38 b, 38 c, and 38 d to the controlcircuit 46 are referred to as F0_RREQ, F1_RREQ, F2_RREQ and F3_RREQrespectively. Further, the acknowledge signals provided from the controlcircuit 46 to each of the FIFO devices 38 a, 38 b, 38 c, and 38 d arereferred to as F0_RACK, F1_RACK, F2_RACK and F3_RACK respectively.

Further, the read addresses of the FIFO devices 38 a, 38 b, 38 c, and 38d are referred to as F0_ADDR, F1_ADDR, F2_ADDR and F3_ADDR respectively.Further, the address of the memory 44 is referred to as MEM_ADDR, andthe write signal controlling the writing of the data to the memory 44 isreferred to as MEM_WRN. Further, a clock signal serving as a referencefor the processing is referred to as CLK, and a state signal indicatinga transition state of the control circuit 46 is referred to as STATE.

Note that, in a case where the request signals F0_RREQ to F3_RREQ aresimultaneously supplied from the FIFO devices 38 a, 38 b, 38 c, and 38 dto the control circuit 46, the control circuit 46 controls theprocessing in sequence starting with the demodulated receive data of thehighest priority finger, according to the predetermined priority orderof fingers 32 a, 32 b, 32 c, and 32 d. The priority order is notrestricted in any way, but in this embodiment, the order goes to lowfrom the finger 32 a, to 32 b, to 32 c, and then to 32 d.

Further, in a case where the request signals F0_RREQ to F3_RREQ aregiven simultaneously, the control circuit 46 controls the processing insequence starting with the highest priority demodulated receive data,according to the predetermined priority order of the demodulated receivedata. The priority order of the demodulated receive data is notrestricted in any way. However, in accordance with this embodiment, theorder goes to low from the demodulated receive data D0 to D3, forexample. Note that, priority may be given to either the priority orderof the fingers 32 a, 32 b, 32 c, and 32 d or the priority order of thedemodulated receive data D0 to D3.

First, referring to the timing chart shown in FIG. 5, an operation in acase of processing the demodulated receive data will be described. Here,following the sequence of the finger 32 a, then 32 b, then 32 c and then32 d, the processing is performed for the demodulated receive data D0 toD3 of the finger 32 a, then for the demodulated receive data D0 to D3 ofthe finger 32 b, then for the demodulated receive data D0 to D3 of thefinger 32 c, and then for the demodulated receive data D0 to D3 of thefinger 32 d.

The demodulated receive data D0 to D3 of the fingers 32 a, 32 b, 32 c,and 32 d are inputted in sequence into their corresponding FIFO devices38 a, 38 b, 38 c, and 38 d and are held there. At this time, the requestsignals F0_RREQ, F1_RREQ, F2_RREQ and F3_RREQ which are outputtedrespectively from the FIFO devices 38 a, 38 b, 38 c, and 38 d to thecontrol circuit 46 change simultaneously to high-level signals, as shownin the timing chart shown in FIG. 5.

The control circuit 46 first changes to the F0 state indicated by thestate signal STATE. In response to this, the demodulated receive data D0read out from the read address F0_ADDR=0 of the FIFO device 38 a isadded together with the data (the initialized data, for example “0”)held in the address MEM_ADDR=0 of the memory 44, and this is held in thesame address MEM_ADDR=0 of the memory 44 at the timing of the falling ofthe write signal MEM_WRN.

After that, the acknowledge signal F0_RACK is supplied from the controlcircuit 46 to the FIFO device 38 a, and it is increased in number to theread address F0_ADDR=1 of the FIFO device 38 a at the timing of thefalling of the acknowledge signal F0_RACK.

The operation is similar thereafter. The demodulated receive data D1 toD3 read out from the read addresses F0_ADDR=1 to 3 of the FIFO device 38a are processed (added cumulatively), and then held in the addressesMEM_ADDR=1 to 3 of the memory 44.

Here, the processing of the demodulated receive data D0 to D3 of theFIFO device 38 a ends, and when the request signal F0_RREQ from the FIFOdevice 38 a changes to a low-level signal, the control circuit 46changes from the F0 state to the F1 state. In this case, as shown in thetiming chart shown in FIG. 5, one clock is required to confirm that therequest signal F0_RREQ from the FIFO device 38 a is a low-level signaland that the request signal F1_RREQ from the FIFO device 38 b is ahigh-level signal, and to change to the F1 state.

Then, in a similar fashion, processing is performed in sequence goingfrom the demodulated receive data D0 to D3 from the FIFO device 38 b,then the demodulated receive data D0 to D3 from the FIFO device 38 c,and the demodulated receive data D0 to D3 from the FIFO device 38 d, andso on.

Here, in the case where four fingers 32 a, 32 b, 32 c, and 32 d areprovided as in this embodiment, the receive data of the maximum fourpaths may be all demodulated simultaneously. Therefore, it is necessaryto add cumulatively the maximum 16 demodulated receive data (=4 data×4fingers) in sequence. In such a case, since two clocks are required forreading/writing the memory 44 for each time that one cumulation additionis performed, the minimum number of clocks required for the processingis 32 clocks.

In contrast, in the example shown in FIG. 5, in order to process one ofthe demodulated receive data, two clocks are required totally. That is,one clock is required to read the data from the memory 44, and one clockis required to write the data to the memory 44, respectively. Further,since one clock is required to change the state of the control circuit46 from one finger to the next finger, 9 clocks are needed for eachfinger, thus requiring processing time of 36 clocks for four fingers intotal.

Therefore, in the case shown in the timing chart shown in FIG. 5, 4 moreclocks are required than the minimum 32 clocks, as described above.Therefore, the frequency of the clock signal CLK is raised so that, forexample, two symbol time units≧36 clocks. Accordingly, the number oflevels in the FIFO devices 38 a, 38 b, 38 c, and 38 d may be, forexample, 5.

Next, referring to the timing chart in FIG. 6, an operation in a case ofthe processing the demodulated receive data will be described. Here,according to a sequence from the receive data D0 to D3, the processingis performed starting with the demodulated receive data D0 of thefingers 32 a, 32 b, 32 c, and 32 d, and then the demodulated receivedata D1 of the fingers 32 a, 32 b, 32 c, and 32 d, then the demodulatedreceive data D2 of the fingers 32 a, 32 b, 32 c, and 32 d, then thedemodulated receive data D3 of the fingers 32 a, 32 b, 32 c, and 32 d,and so on.

The demodulated receive data D0 to D3 from the fingers 32 a, 32 b, 32 c,and 32 d are inputted in sequence into their corresponding FIFO devices38 a, 38 b, 38 c, and 38 d and are held there. At this time, the requestsignals F0_RREQ, F1_RREQ, F2_RREQ and F3_RREQ which are outputtedrespectively from the FIFO devices 38 a, 38 b, 38 c, and 38 d to thecontrol circuit 46 change simultaneously to high-level signals, as shownin the timing chart shown in FIG. 6.

The control circuit 46 first changes to the F0 state. In response tothis, the demodulated receive data D0 read out from the read addressF0_ADDR=0 of the FIFO device 38 a is added together with the data (theinitialized data, for example “0”) held in the address MEM_ADDR=0 of thememory 44, and this is held in the same address MEM_ADDR=0 of the memory44 at the falling timing of the write signal MEM_WRN.

After that, the acknowledge signal F0_RACK is provided from the controlcircuit 46 to the FIFO device 38 a, it is increased in number to theread address F0_ADDR=1 at the falling timing of the acknowledge signal.Further, at the control circuit 46, the priority order of the finger 32a is set as the lowest (last) priority. Accordingly, the finger 32 b isautomatically set as the highest priority order, and the control circuit46 enters the F1 state.

In other words, in the case of the example shown in FIG. 6, there is anadvantage that, in order to change the state of the control circuit 46from a finger to the next finger, one clock is not required as in theexample shown in FIG. 5. Note that, when logical function descriptionlanguage such as a state machine or other is used to perform the logicaldesign of the control circuit 46, there is an advantage that one onlyneeds to specify that the priority order of each finger 32 a, 32 b, 32c, and 32 d is shifted to the lowest priority after the processing hasended, which is extremely simple.

The subsequent processing is similar. The demodulated receive data D0 ofthe FIFO devices 38 b, 38 c and 38 d are processed. Next, the processingfor the demodulated receive data D1 of the FIFO devices 38 a, 38 b, 38c, and 38 d, the demodulated receive data D2 of the FIFO devices 38 a,38 b, 38 c, and 38 d, and the demodulated receive data D3 of the FIFOdevices 38 a, 38 b, 38 c, and 38 d are performed in sequence. When theprocessing for the demodulated receive data D3 of the FIFO devices 38 a,38 b, 38 c, and 38 d is finished, the corresponding request signalsF0_RREQ to F3_RREQ change to low-level signals.

In the case of the example shown in FIG. 6, in order to process one ofthe demodulated receive data, one clock is required to read the datafrom the memory 44, and one clock is needed to write the data to thememory 44, respectively, thus requiring a total of two clocks. Further,since one clock is not required to change the state of the controlcircuit 46 from one finger to the next finger, the processing can becompleted in 8 clocks for each of the fingers, that is, in a total of 32clocks for four fingers, which is the minimum number of clocks.

Therefore, in the case of the example shown in FIG. 6, since theprocessing can be completed in the minimum of 32 clocks, the frequencyof the clock signal CLK can be reduced so that two symbol time units=32clocks, to reduce the power consumption more than in the case of theexample shown in FIG. 5. Further, in the case of this embodiment, sincethe number of levels of the FIFO devices 38 a, 38 b, 38 c, and 38 d canbe set at minimum number of 4, there is an advantage that the scale ofthe circuitry for the FIFO can be kept at a minimum.

Note that, in the above-mentioned explanation of the operation, the STTDused in the 3GPP is described by giving an example of the case in whichthe demodulated receive data is sequentially inputted into the FIFOdevices 38 a, 38 b, 38 c, and 38 d in units composed of four receivedata. However, the present invention is not restricted to this example,and one receive data may serve as the unit from the finger to the FIFO,or two or more receive data may serve as the unit to be inputted.

The RAKE receiver device according to the present invention is basicallyas described above.

Note that, the constructions of the data synthesis circuits 14 and 36are not restricted to the examples shown in the diagram, but may haveother circuitry structures for realizing the same functions.

Detailed description of the RAKE receiver device according to thepresent invention has been given above, but the present invention is notrestricted to the above-mentioned embodiment, and various improvementsand alterations may be made without departing from the gist of theessence of the present invention.

INDUSTRIAL APPLICABILITY

As described in detail above, in the RAKE receiver device according tothe present invention, each time the receive data is demodulated by oneof the plurality of fingers, the data synthesis circuit addscumulatively the demodulated receive data for each identical data ofeach of the paths and synthesizes the data. Further, each time thereceive data of the respective paths having been demodulated by thefingers are supplied from the timing adjustment circuit, the datasynthesis circuit adds cumulatively the demodulated receive data foreach identical receive data of the respective paths, and synthesizes thedata.

As a result, in accordance with the RAKE receiver device of the presentinvention, the necessary memory capacity for the RAKE synthesis can bereduced by up to (1/number of fingers) as compared to the conventionaltechnique, thus enabling the reduction in the scale of the circuitry,and moreover, the reduction in the consumed power.

1. A RAKE receiver device comprising: a plurality of fingers fordemodulating receive data of multiple paths; a data synthesis circuitfor synthesizing the receive data from each of the paths and demodulatedby the plurality of fingers; and a timing adjustment circuit foradjusting timing when the receive data from each of the paths anddemodulated by the plurality of fingers are provided to the datasynthesis circuit, wherein the timing adjustment circuit holds thereceive data from each of the paths and demodulated by the fingers, andeach time that the receive data from each of the paths are demodulatedby the plurality of fingers are supplied from the timing adjustmentcircuit, the data synthesis circuit adds cumulatively the demodulatedreceive data for each identical receive data from each of the paths, andsynthesizes the data.
 2. A RAKE receiver device, comprising, a pluralityof fingers for demodulating receive data of multiple paths; a datasynthesis circuit for synthesizing the receive data from each of thepaths and demodulated by the plurality of fingers, wherein each timethat the receive data from each of the path is demodulated by one of theplurality of fingers, the data synthesis circuit adds cumulatively thedemodulated receive data for each identical receive data from each ofthe paths, and synthesizes the data; and wherein the data synthesiscircuit comprises one memory that is shared by the fingers, and eachtime the receive data from each of the paths are demodulated by theplurality of fingers, cumulatively added data is read out from eachcorresponding memory address, added to the demodulated identical receivedata from each of the paths, and written back into the same respectivelycorresponding address of the memory.
 3. A RAKE receiver device,comprising; a plurality of fingers for demodulating receive data ofmultiple paths, wherein the fingers are set in advance with priorityorder; a data synthesis circuit for synthesizing the receive data fromeach of the paths and demodulated by the plurality of fingers, whereineach time that the receive data of each path is demodulated by one ofthe plurality of fingers, the data synthesis circuit adds cumulativelythe demodulated receive data for each identical receive data from eachof the paths, and synthesizes the data; and wherein the data synthesiscircuit adds cumulatively, one at a time and in chronological order, theidentical receive data from each of the paths and demodulated by theplurality of fingers, and when two or more demodulated receive data fromeach of the paths are inputted simultaneously, the data synthesiscircuit sequentially adds cumulatively the demodulated receive data fromeach of the paths for each identical receive data, according to thepriority order.
 4. A RAKE receiver device comprising: a plurality offingers for demodulating receive data from multiple paths; a datasynthesis circuit for synthesizing the receive data from each of thepaths and demodulated by the plurality of fingers; and a timingadjustment circuit for adjusting timing when the receive data from eachof the paths and demodulated by the plurality of fingers are provided tothe data synthesis circuit, wherein the plurality of fingers demodulatea plurality of receive data per one symbol time unit, the timingadjustment circuit holds the plurality of receive data from each of thepaths and demodulated by the plurality of fingers, and each time thatthe receive data from each of the paths and demodulated by the pluralityof fingers are supplied from the timing adjustment circuit, the datasynthesis circuit adds cumulatively the demodulated receive data foreach identical receive data from each of the paths, and synthesizes thedata.
 5. A RAKE receiver device according to claim 4, wherein the datasynthesis circuit comprises one memory shared by the plurality offingers, each time that the receive data from each of the paths anddemodulated by the plurality of fingers are supplied from the timingadjustment circuit, cumulatively added data is read out from eachcorresponding memory address, added to the demodulated identical receivedata from each of the paths, and written back into the same respectivelycorresponding address of the memory.
 6. A RAKE receiver device accordingto claim 4, wherein the plurality of fingers and the plurality ofreceive data are each set in advance with priority order, the datasynthesis circuit receives from the timing adjustment circuit thedemodulated receive data from each of the paths and adds cumulativelythem one at a time and in chronological order, when two or more of thedemodulated receive data from each of the paths are held in the timingadjustment circuit, the data synthesis circuit sequentially receives,from the timing adjustment circuit, the same-priority-order demodulatedreceive data of the plurality of fingers according to the priority orderof the fingers, further repeats this operation according to the priorityorder of the receive data, and sequentially adds cumulatively thedemodulated receive data from each of the paths for each identicalreceive data.
 7. A RAKE receiver device according to claim 1, whereinthe data synthesis circuit comprises one memory that is shared by thefingers, and each time the receive data from each of the paths aredemodulated by the plurality of fingers, cumulatively added data is readout from each corresponding memory address, added to the demodulatedidentical receive data from each of the paths, and written back into thesame respectively corresponding address of the memory.
 8. A RAKEreceiver device according to claim 1, wherein the fingers are set inadvance with priority order, the data synthesis circuit addscumulatively, one at a time and in chronological order, the identicalreceive data from each of the paths and demodulated by the plurality offingers, and when two or more demodulated receive data from each of thepaths are inputted simultaneously, the data synthesis circuitsequentially adds cumulatively the demodulated receive data from each ofthe paths for each identical receive data, according to the priorityorder.
 9. A RAKE receiver device according to claim 2, wherein thefingers are set in advance with priority order, the data synthesiscircuit adds cumulatively, one at a time and in chronological order, theidentical receive data from each of the paths and demodulated by theplurality of fingers, and when two or more demodulated receive data fromeach of the paths are inputted simultaneously, the data synthesiscircuit sequentially adds cumulatively the demodulated receive data fromeach of the paths for each identical receive data, according to thepriority order.
 10. A RAKE receiver device according to claim 5, whereinthe plurality of fingers and the plurality of receive data are each setin advance with priority order, the data synthesis circuit receives fromthe timing adjustment circuit the demodulated receive data from each ofthe paths and adds cumulatively them one at a time and in chronologicalorder, when two or more of the demodulated receive data from each of thepaths are held in the timing adjustment circuit, the data synthesiscircuit sequentially receives, from the timing adjustment circuit, thesame-priority-order demodulated receive data of the plurality of fingersaccording to the priority order of the fingers, further repeats thisoperation according to the priority order of the receive data, andsequentially adds cumulatively the demodulated receive data from each ofthe paths for each identical receive data.